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Display IP

Display IP

퀄리타스반도체는 디스플레이 칩셋 (Display Chipset)을 위한 다양한 HSI IP를 제공합니다. ​디스플레이 패널 제품이 다변화됨에 따라 응용분야가 다양해지고 있어, Display Chipset 역시 새로운 성장동력을 얻고 있습니다. 4K UHD에 이어 8K UHD 해상도를 지원하는 디스플레이 기기들의 출시로 더 선명한 화질과 해상도로 정보를 전달할 수 있습니다. 대표적인 디스플레이 칩셋은 크게 DTV SoC, TCON IC, DDI가 있으며 더 높은 해상도와 고화질 데이터를 전송하기 위한 초고속 인터페이스 IP와 디스플레이 칩셋 개발은 퀄리타스반도체의 중요한 과제 중 하나입니다.

퀄리타스반도체는 TCON 인터페이스의 대표적인 표준인 eDP 그리고 TCON IC에서 패널을 구동하는 DDI로 영상 신호를 전송하기 위한 Intra-Panel 인터페이스를 제공하고 있습니다.

eDP RX Intra-Panel

eDP RX PHY

Request Datasheet

The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures. With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification. This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.

Features

  • Compliant to DisplayPort v1.4, eDP v1.4b, and eDP v1.5a
  • Supports data rates from Reduced Bit Rate ( RBR :1.62 Gbps) to High Bit Rate 3 
    ( HBR3 :8.1 Gbps), and user configurable custom B/Ws
  • Supports for eDP v1.4b features, such as PSR1 and PSR2
  • Supports eDP v1.5a features, including AUX-less link training ( Low Frequency Periodic Signaling )
  • Adaptive Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
  • Automatic calibration of analog circuits and parametric offset cancellation
  • Supports Built in Eye Open Monitor feature
  • Built In Self Test (BIST), including DP Standard Training Pattern Sets (TPS1~TPS4), pseudo random bit stream generation and checkers
  • Includes PCS layer for easier link interfaces (symbol aligning, 8b10b decoder, de-scrambler, and support for fail-safe auto recovery feature )
  • AUX Rx controller includes sync detection and fully synthesizable digital CDR 
  • Operating parameters can be fully configured by APB v3.0 and SPI interfaces

Tech Specs

Foundry Node 14 nm
Standard eDP v1.4b eDP v1.5a
Max. datarate Under NDA
Status

Intra-Panel TX PHY

Request Datasheet

Qualitas' Intra-panel TX PHY IP is an advanced chip-on-glass (ACOG) and chip-on-film (COF) transmitter embedded into the timing controller for TFT-LCD panels. This technology enables a single chip to support multiple display interfaces, reducing system costs and complexity. It also provides higher data transfer rates, lower power consumption, and compatibility with a wide range of devices.

Features

  • Supports data rates from 120 Mbps to a maximum of 4 Gbps
  • Supports Power Down and Low-Power modes during V-blank period
  • Programmable differential transmitter output impedance (75 ohm ~ 180 ohm)
  • Programmable differential transmitter output amplitude (up to 6 dB)
  • Jitter Injector Includes jitter Injector for debugging purposes
  • Built-in self-test (BIST) including pseudo random bit stream (PRBS) generation and checker

Tech Specs

Foundry Node 28 nm 14 nm 8 nm
Standard Under NDA
Max. datarate
Status