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MIPI

MIPI

クオリタス半導体は、広く使用されるCSIとDSIインターフェイスの 仕様を含め、モバイルやIoT、自動車産業向けのMIPI IPソリューションを 多数提供しています。MIPI(Mobile Industry Processor Interface)規格は、 モデム・AP・カメラ・ディスプレイ・オーディオ・ストレージ・アンテナ・ チューナーなどモバイル機器に搭載されるすべての半導体部品間の超高速 インターコネクトを対象にしており、現在では、ほぼすべてのモバイル 機器はもちろん、AIや自動運転などの応用分野にも広がっています。

クオリタス半導体は、28nm CMOSをはじめとする8nm・5nm・4nm 工程のD/C-PHY Combo PHY IPなど様々なFinFET半導体工程にMIPI IPを 提供しています。

PHY IP Controller IP

MIPI D-PHY

Request Datasheet

Qualitas' MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low-power solution.

Features

  • Fully supports MIPI D-PHY HS-TX, HS-RX, LP-TX, LP-RX, and ULPS
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test feature producing and checking PRBS random pattern
  • Low-power consumption and small area
  • Highly validated structure in various processes

Tech Specs

Foundry Node 28 nm 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
Status

MIPI C-PHY

Request Datasheet

The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low power solution.

Features

  • Fully supports MIPI HS-TX, HS-RX, LP-TX, LP-RX, ULPS, and ALP
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test features producing and checking PRBS random pattern

Tech Specs

Foundry Node 28 nm 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
Status

MIPI D-PHY/C-PHY Combo

Request Datasheet

Qualitas' MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low-power solution.

Features

  • Fully supports MIPI D-PHY HS-TX, HS-RX, LP-TX, LP-RX, and ULPS
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test feature producing and checking PRBS random pattern
  • Low-power consumption and small area
  • Highly validated structure for processes below 8 nm

Tech Specs

Foundry Node 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
(D-PHY)
Max. datarate
(C-PHY)
Status

CSI-2 RX Controller

Request Datasheet

The Qualitas CSI-2 RX controller IP is optimized for low power, small size and high-speed interfaces, supporting a wide range of higher image resolutions. The CSI-2 RX Controller IP is fully compliant with the CSI-2 v1.2 specification and supports the DPHY v2.0 and CPHY v1.2.

Features

  • Compliant with the MIPI CSI-2 v1.2 specification
  • PHY interface features
    Supports MIPI DPHY v2.0, 1 to 4 DPHY data lanes
    Supports MIPI CPHY v1.2, 1 to 3 CPHY data trios
    Supports ULPS Mode
  • Link layer features
    Supports DPHY or CPHY based on user configuration
    Provides lane merging, error detection and correction, virtual channel detection, programmable data extraction and embedded data separation
    Supports all packet level errors and protocol decoding level errors
    Supports the following pixel formats : RGB888, Loosely Packed RGB666, RGB565, YUV422 (8bit)

DSI TX/RX Controller

Request Datasheet

The Qualitas DSI TX/RX controller IP is optimized for low power, small size and high-speed interfaces between an application processor and display modules using either MIPI CPHY or MIPI DPHY. The DSI TX/RX Controller IP is fully compliant with the DSI v1.3 specification and supports the DPHY

Features

  • Compliant with the following MIPI specifications
    MIPI DSI specification v1.3
    MIPI D-PHY Specification v1.2
    Display Pixel Interface (DPI-2) v2.0
    Display Bus Interface (DBI) v2.0
    Display Command Set (DCS) v1.3
  • PHY interface features
    Supports MIPI DPHY v1.2, 1 to 4 DPHY data lanes
    Supports MIPI CPHY v1.2, 1 to 3 CPHY data trios
    Supports ULPS/LPDT/LPDR/BTA mode
  • Link layer features
    Multiple peripheral support capability with configurable virtual channels
    ECC and checksum capabilities
    Supports the following pixel formats : RGB565, RGB666 packed and loosely, RGB888