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PCle

PCI express PHY

クオリタス半導体は、PCIe(Peripheral Component Interconnect Express) ソリューションに焦点を当てた超高速インターコネクト技術を 提供いたします。PCIe規格とは様々な周辺機器に接続するための インターコネクト技術で、最新バージョンにアップデートされる度に データ伝送速度が倍増します。バージョン6.0では、64 Gbpsに上る超高速 伝送を提供いたします。AIや自動車、データセンター、ストレージ、 モバイルなど様々な分野で高帯域幅・低遅延通信の需要 が増加するに伴って、その活用が広がっています。

クオリタス半導体は8 nm FinFET工程においてPCIe 4.0 PHY IPを 提供しており、14 nm・5 nm・4 nm工程にも拡張する方針です。 また、 5 nm工程においてはDSPベースのPCIe 6.0 PHYを開発しています。

PCle 6.0 PHY PCle 4.0 PHY

PCle 6.0

Request Datasheet

Qualitas' PCIe 6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using FinFET CMOS technology. It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

Features

  • compliant with PCIe Base 6.0 and PIPE 6.2
  • Supports Gen1, Gen2, Gen3, Gen4, Gen5 and Gen6
  • Lane configuration
    Common (CMN) and 1, 2 or 4 Data Lanes
  • Supports high-resolution multi-tap FFE in transmitter
  • Supports CTLE, DSP-based multi-tap FFE and 1-tap DFE for channel equalization in receiver
  • Supports adaptive channel equalization
  • Requires a 100 MHz reference clock is required (with support for differential input buffer)
  • Built-in self test feature capable of generating and checking PRBS patterns
  • PCS included in PHY hardmacro

Tech Specs

Foundry Node 5 nm
Standard Under NDA
Max. datarate
Status

PCle 4.0

Request Datasheet

Qualitas' PCIe 4.0 PHY IP consists of hardmacro PMA and softmacro PCS compliant with PCIe Base 4.0 specification. This IP offers a cost-effective and low-power solution using FinFET CMOS technology. It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

Features

  • compliant with PCIe Base 4.0 and PIPE 4.4.1 specification
  • Supports Gen1, Gen2, Gen3 and Gen4
  • Lane configuration
    Common (CMN) and  1, 2 or 4 Data Lanes
  • Supports both aggregation and bifurcation modes (5nm PCIe 4.0 PHY only)
    4-Lane PHY: 4-Lane aggregation or 2-Lane/2-Lane bifurcation
    2-Lane PHY: 2-Lane aggregation or 1-Lane/1-Lane bifurcation
  • Supports high-resolution multi-tap FFE in transmitter
  • Supports CTLE and 5-tap DFE for channel equalization in receiver
  • Supports adaptive channel equalization
  • Requires a 100 MHz reference clock is required (with support for differential input buffer)
  • Built-in self test feature capable of generating and checking PRBS patterns
  • Compatible PCS is supports in softmacro form

Tech Specs

Foundry Node 8 nm 5 nm
Standard Under NDA
Max. datarate
Status