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Display IP

Display IP

快丽达斯 半导体为显示器芯片组（Display Chipset）提供了多种HSI IP。​ 随着显示器面板的多元化，其应用领域也在出现多样化的趋势， 这也给显示器芯片组注入了新的增长动力。继4K超高清显示器的问世， 8K超高清产品的相继推出，将带给您更清晰的画面信息。 典型的显示器芯片组可分为DTV SoC、TCON IC和DDI等。 快丽达斯 半导体的重要任务之一就是研发高速接口IP和显示器芯片组， 为更高的分辨率和高画质数据传输提供支撑。

快丽达斯 半导体提供典型TCON接口的标准eDP和从TCON IC到驱动面板的DDI传输影像信号的Intra-Panel接口。

eDP RX Intra-Panel

eDP RX PHY

Request Datasheet

The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures. With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification. This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.

Features

  • Compliant to DisplayPort v1.4, eDP v1.4b, and eDP v1.5a
  • Supports data rates from Reduced Bit Rate ( RBR :1.62 Gbps) to High Bit Rate 3 
    ( HBR3 :8.1 Gbps), and user configurable custom B/Ws
  • Supports for eDP v1.4b features, such as PSR1 and PSR2
  • Supports eDP v1.5a features, including AUX-less link training ( Low Frequency Periodic Signaling )
  • Adaptive Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
  • Automatic calibration of analog circuits and parametric offset cancellation
  • Supports Built in Eye Open Monitor feature
  • Built In Self Test (BIST), including DP Standard Training Pattern Sets (TPS1~TPS4), pseudo random bit stream generation and checkers
  • Includes PCS layer for easier link interfaces (symbol aligning, 8b10b decoder, de-scrambler, and support for fail-safe auto recovery feature )
  • AUX Rx controller includes sync detection and fully synthesizable digital CDR 
  • Operating parameters can be fully configured by APB v3.0 and SPI interfaces

Tech Specs

Foundry Node 14 nm
Standard eDP v1.4b eDP v1.5a
Max. datarate Under NDA
Status

Intra-Panel TX PHY

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Qualitas' Intra-panel TX PHY IP is an advanced chip-on-glass (ACOG) and chip-on-film (COF) transmitter embedded into the timing controller for TFT-LCD panels. This technology enables a single chip to support multiple display interfaces, reducing system costs and complexity. It also provides higher data transfer rates, lower power consumption, and compatibility with a wide range of devices.

Features

  • Supports data rates from 120 Mbps to a maximum of 4 Gbps
  • Supports Power Down and Low-Power modes during V-blank period
  • Programmable differential transmitter output impedance (75 ohm ~ 180 ohm)
  • Programmable differential transmitter output amplitude (up to 6 dB)
  • Jitter Injector Includes jitter Injector for debugging purposes
  • Built-in self-test (BIST) including pseudo random bit stream (PRBS) generation and checker

Tech Specs

Foundry Node 28 nm 14 nm 8 nm
Standard Under NDA
Max. datarate
Status