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SERDES

100G SERDES PHY

为攻克运转速率和带宽的瓶颈， 快丽达斯 半导体正致力于研发最先进的SERDES PHY设计技术。100G SERDES PHY IP提供在各种高速互连规格所需的核心功能。数据传输编码方式中，相比不归零编码 (Non-Return to Zero, NRZ)， 对四阶脉衝振幅调变(Pulse Amplitude Modulation with 4 levels, PAM4) 编码的需求正在不断增加。快丽达斯 半导体也通过以太网（Ethernet） 和PCIe，采用PAM4正在进一步提高数据的传输速率。

快丽达斯 半导体同时研发模拟CDR和DSP两种方式的100G SERDES PHY IP， 并根据客户的应用领域提供最优化的解决方案。 我司将依托新一代技术，在高速互连领域进一步拓展业务。

100G PAM4 SERDES PHY

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Qualitas' 100G SERDES PHY IP for VSR supports up to 100 Gbps data rate with low-power consumption and a small footprint. It has advanced features such as equalization, and clock and data recovery, ensuring reliable data transmission. The IP can be integrated into a variety of applications such as networking, data centers, and high-performance computing.

Features

  • Up to 12 dB of insertion loss
  • Common (CMN) and 1, 2 or 4 Data Lanes
  • Supports 100 and 50G PAM4 and 50 and 25G NRZ
  • RX CTLE/VGA and TX FIR Filters for Channel Equalization

Tech Specs

Foundry Node 14 nm
Standard Under NDA
Max. datarate
Status