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MIPI

MIPI

快丽达斯 半导体提供广泛使用的CSI及DSI接口配置等专为移动、 物联网和汽车产业设计的多种MIPI IP解决方案。 移动产业处理器接口（Mobile Industry Processor Interface，MIPI） 适用于调制解调器、AP、摄像头、显示器、音频、存储、天线、 调谐器等移动设备所有半导体之间的高速互连。如今，除所有移动设备， MIPI的应用领域还在进一步延申到人工智能和自动驾驶等领域。

快丽达斯 半导体可在28nm CMOS和8nm、5nm、4nm工艺的 D/C-PHY Combo PHY IP等各种鳍式场效应晶体管工艺中提供MIPI IP。

PHY IP Controller IP

MIPI D-PHY

Request Datasheet

Qualitas' MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low-power solution.

Features

  • Fully supports MIPI D-PHY HS-TX, HS-RX, LP-TX, LP-RX, and ULPS
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test feature producing and checking PRBS random pattern
  • Low-power consumption and small area
  • Highly validated structure in various processes

Tech Specs

Foundry Node 28 nm 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
Status

MIPI C-PHY

Request Datasheet

The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low power solution.

Features

  • Fully supports MIPI HS-TX, HS-RX, LP-TX, LP-RX, ULPS, and ALP
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test features producing and checking PRBS random pattern

Tech Specs

Foundry Node 28 nm 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
Status

MIPI D-PHY/C-PHY Combo

Request Datasheet

Qualitas' MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. In addition, extensive built-in self-test features, such as loopback and scan, are supported. It offers a cost-effective and low-power solution.

Features

  • Fully supports MIPI D-PHY HS-TX, HS-RX, LP-TX, LP-RX, and ULPS
  • Supports lane configurations according to the user's demands
  • Global operation timing parameters control
  • Backward compatible with previous versions
  • Built-in self-test feature producing and checking PRBS random pattern
  • Low-power consumption and small area
  • Highly validated structure for processes below 8 nm

Tech Specs

Foundry Node 14 nm 8 nm 5 nm 4 nm
Standard Under NDA
Max. datarate
(D-PHY)
Max. datarate
(C-PHY)
Status

CSI-2 RX Controller

Request Datasheet

The Qualitas CSI-2 RX controller IP is optimized for low power, small size and high-speed interfaces, supporting a wide range of higher image resolutions. The CSI-2 RX Controller IP is fully compliant with the CSI-2 v1.2 specification and supports the DPHY v2.0 and CPHY v1.2.

Features

  • Compliant with the MIPI CSI-2 v1.2 specification
  • PHY interface features
    Supports MIPI DPHY v2.0, 1 to 4 DPHY data lanes
    Supports MIPI CPHY v1.2, 1 to 3 CPHY data trios
    Supports ULPS Mode
  • Link layer features
    Supports DPHY or CPHY based on user configuration
    Provides lane merging, error detection and correction, virtual channel detection, programmable data extraction and embedded data separation
    Supports all packet level errors and protocol decoding level errors
    Supports the following pixel formats : RGB888, Loosely Packed RGB666, RGB565, YUV422 (8bit)

DSI TX/RX Controller

Request Datasheet

The Qualitas DSI TX/RX controller IP is optimized for low power, small size and high-speed interfaces between an application processor and display modules using either MIPI CPHY or MIPI DPHY. The DSI TX/RX Controller IP is fully compliant with the DSI v1.3 specification and supports the DPHY

Features

  • Compliant with the following MIPI specifications
    MIPI DSI specification v1.3
    MIPI D-PHY Specification v1.2
    Display Pixel Interface (DPI-2) v2.0
    Display Bus Interface (DBI) v2.0
    Display Command Set (DCS) v1.3
  • PHY interface features
    Supports MIPI DPHY v1.2, 1 to 4 DPHY data lanes
    Supports MIPI CPHY v1.2, 1 to 3 CPHY data trios
    Supports ULPS/LPDT/LPDR/BTA mode
  • Link layer features
    Multiple peripheral support capability with configurable virtual channels
    ECC and checksum capabilities
    Supports the following pixel formats : RGB565, RGB666 packed and loosely, RGB888