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PCle

PCI express PHY

快丽达斯 半导体依托高速串行计算机扩展总线标准（Peripheral Component Interconnect Express，PCIe） 方案提供强有力的高速互连技术。 PCIe是连接各种外围设备的互连技术， 每升级一个版本，其数据传输速率就会增加一倍，PCIe 6.0版本可实现 64 Gbps的超高传输速率。 随着人工智能、汽车、数据中心、存储、 移动等各领域对高带宽和低延迟通信的需求不断增加， PCIe的应用范围正不断延申。

快丽达斯 半导体正在8 nm鳍式场效应晶体管工艺提供PCIe 4.0 PHY IP， 并计划进一步延申到14 nm、5 nm和4nm工艺。 此外，我们还在5 nm工艺研发以DSP为核心的PCIe 6.0 PHY。​

PCle 6.0 PHY PCle 4.0 PHY

PCle 6.0

Request Datasheet

Qualitas' PCIe 6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using FinFET CMOS technology. It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

Features

  • compliant with PCIe Base 6.0 and PIPE 6.2
  • Supports Gen1, Gen2, Gen3, Gen4, Gen5 and Gen6
  • Lane configuration
    Common (CMN) and 1, 2 or 4 Data Lanes
  • Supports high-resolution multi-tap FFE in transmitter
  • Supports CTLE, DSP-based multi-tap FFE and 1-tap DFE for channel equalization in receiver
  • Supports adaptive channel equalization
  • Requires a 100 MHz reference clock is required (with support for differential input buffer)
  • Built-in self test feature capable of generating and checking PRBS patterns
  • PCS included in PHY hardmacro

Tech Specs

Foundry Node 5 nm
Standard Under NDA
Max. datarate
Status

PCle 4.0

Request Datasheet

Qualitas' PCIe 4.0 PHY IP consists of hardmacro PMA and softmacro PCS compliant with PCIe Base 4.0 specification. This IP offers a cost-effective and low-power solution using FinFET CMOS technology. It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

Features

  • compliant with PCIe Base 4.0 and PIPE 4.4.1 specification
  • Supports Gen1, Gen2, Gen3 and Gen4
  • Lane configuration
    Common (CMN) and  1, 2 or 4 Data Lanes
  • Supports both aggregation and bifurcation modes (5nm PCIe 4.0 PHY only)
    4-Lane PHY: 4-Lane aggregation or 2-Lane/2-Lane bifurcation
    2-Lane PHY: 2-Lane aggregation or 1-Lane/1-Lane bifurcation
  • Supports high-resolution multi-tap FFE in transmitter
  • Supports CTLE and 5-tap DFE for channel equalization in receiver
  • Supports adaptive channel equalization
  • Requires a 100 MHz reference clock is required (with support for differential input buffer)
  • Built-in self test feature capable of generating and checking PRBS patterns
  • Compatible PCS is supports in softmacro form

Tech Specs

Foundry Node 8 nm 5 nm
Standard Under NDA
Max. datarate
Status